In this blog, we’ll explore how to integrate XADC with UberDDR3 for thermal management. By monitoring temperature, UberDDR3 can automatically reset when things get too hot, ensuring the system stays aligned and functions properly. We’ll walk through both a simulation and a project demo on the ArtyS7 FPGA board to show how this solution works in practice.
Table of Contents: I. MIG Implementation of Thermal Management
I. MIG Implementation of Thermal Management
In the "Temperature Monitor" section of the UG586 MIG User Guide (available here), the document explains:
"The temperature monitor helps maintain DQS center alignment in the data valid window by compensating for temperature drift"
"The temperature monitor is comprised of two modules. The first module, tempmon, instantiates the XADC module and periodically samples it for the current device temperature "
Essentially, the MIG DDR3 controller uses an XADC module to monitor the internal temperature of the device. Why? Because as the temperature changes, it can cause slight shifts in the timing of DDR3 signals. These shifts might result in the DQS (data strobe signal) drifting out of alignment with the data valid window, which could lead to errors.
To address this, the MIG dynamically adjusts the PHASER_IN and PHASER_OUT components. These phasers handle the delay of incoming and outgoing signals, ensuring that the DQS stays properly aligned—even as temperature fluctuates.
II. UberDDR3 with XADC Implementation
Adding an XADC to interact with UberDDR3 is straightforward and entirely feasible. However, replicating the capability to adjust PHASER_IN/OUT is not possible because UberDDR3's PHY uses IODELAY instead. PHASER_IN/OUT are undocumented Xilinx IPs, and there is no publicly available information on how they determine adjustments for high temperatures (e.g., specific phase shifts or delay taps per degree Celsius).
Since IODELAY does not provide any built-in mechanism for temperature-based adjustments, UberDDR3 cannot dynamically adjust the DQS center alignment based on temperature changes.
The simplest and most effective solution is to reset UberDDR3 whenever the XADC detects that the temperature has exceeded a set limit. During the reset, the calibration sequence will restart, realigning the DQS. Alternatively, UberDDR3 can remain in the reset state until the temperature drops back below the critical threshold. We’ll use the second approach for now since it’s simpler, while reserving the first approach for future implementation.
III. Simulation Testbench
For simulation, follow these steps to get started:
1. First, clone the UberDDR3 repository using the following command:
2. Create a new Vivado project:
Open Vivado and create a new project.
Add the design directory rtl/ to the project as your design source.
3. Add the testbench/ directory to the project as a simulation source:
Add design.txt from the testbench/ folder. This contains the analog stimulus file for simulation:
4. Open the XADC Wizard from the IP Catalog and configure it as follows:
Use a single channel for temperature monitoring and set the timing mode to continuous so the XADC samples and updates the temperature automatically.
Under DRP Timing Options, ensure Enable DCLK is checked. Set the DCLK frequency to 100 MHz. If unchecked, the simulation may fail.
Keep the Analog Sim File Options set to default. This links the design.txt file containing the stimulus.
In the Alarms tab, enable only the User Temperature Alarm and set the trigger to 50°C. This will assert the user_temp_alarm_out signal, which resets UberDDR3. For demonstration purposes on the ArtyS7 FPGA board, 50°C was used (the temperature often reaches ~47°C). However, for real applications, a higher threshold like 80°C is recommended, as the DDR3 self-refresh operates up to 85°C.
Open ddr3_dimm_micron_sim module under Simulation Sources. Make sure the defines are as shown below:
Ensure XADC is defined. The XADC will receive the 100 MHz i_controller_clk and output the user_temp_alarm_out signal:
Shown below is how the user_temp_alarm_out is connected to i_rst_n of UberDDR3. Basically. when user_temp_alarm_out asserts high, UberDDR3 will be reset. Only when user_temp_alarm_out deasserts will UberDDR3 be released from reset:
6. Set ddr3_dimm_micron_sim as top module for Simulation Sources, the hierarchy must be as shown below:
7. Add waveform configuration file ddr3_dimm_micron_sim_behav.wcfg:
8. Click on Run Simulation and analyze the results:
At ~36 µs and ~71 µs, user_temp_alarm_out asserts, causing i_rst_n of UberDDR3 to go low, initiating a reset.
When user_temp_alarm_out deasserts at ~51 µs and ~81 µs, i_rst_n goes high, releasing UberDDR3 from reset.
The initial_calibration_done signal asserts once the write and read calibration is completed. However, it deasserts when user_temp_alarm_out asserts, and reasserts after i_rst_n has remained high for a while.
The eoc_out signal from XADC indicates the end-of-conversion. Since the XADC operates in continuous mode, it continuously converts the temperature readings.
IV. Project Demonstration
Now let’s implement the XADC+UberDDR3 integration on an FPGA board! For this demonstration, we’ll use the ArtyS7 FPGA board:
1. Add the directory example_demo/arty_s7 as source files:
On module arty_ddr3.v, you will notice the same XADC instantiation we used in the simulation:
Check the Design Sources hierarchy, which should look as follows:
2. Run Synthesis-to-Bitstream Generation in Vivado. Then, connect the ArtyS7 FPGA board to your computer, and download the generated bitstream onto the board.
3. In the Hardware Manager tab of Vivado, click on the XADC (System Monitor) to display the live temperature readings of the ArtyS7 FPGA board.
As shown below, the system starts at 48.2°C, which is below the set limit of 50°C. If you check the ArtyS7 board, you’ll see three LEDs are lit, indicating that UberDDR3 is operational and has completed its calibration:
After a short wait, the temperature rises and hits the 50°C limit. When this happens:
The three LEDs turn off.
One LED turns on, indicating that UberDDR3 has entered a reset state.
This simple project demonstrates how easy it is to use the XADC IP to monitor temperature and trigger UberDDR3 to shut down when it exceeds a critical limit.
V. Conclusion
This project shows how easy it is to use the XADC to keep UberDDR3 running smoothly by monitoring temperature. When things heat up, UberDDR3 takes a break and resets itself, ensuring everything stays aligned. In this blog, we not only simulated the design but also implemented a project demo on the ArtyS7 FPGA board, showing how this simple yet effective approach handles thermal management in both virtual and real-world scenarios.
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